High performance synchronous digital processing systems utilize pipelining to increase parallel performance and throughput. In synchronous systems, pipelining results in many partitioned or subdivided smaller blocks or stages and a system clock is applied to registers between the blocks/stages. The system clock initiates movement of the processing and data from one stage to the next, and the processing in each stage must be completed during one fixed clock cycle. When certain stages take less time than a clock cycle to complete processing, the next processing stages must wait—increasing processing delays (which are additive).
In contrast, asynchronous systems (i.e., clockless) do not utilize a system clock and each processing stage is intended, in general terms, to begin its processing upon completion of processing in the prior stage. Several benefits or features are present with asynchronous processing systems. Each processing stage can have a different processing delay, the input data can be processed upon arrival, and consume power only on demand.
FIG. 1 illustrates a prior art Sutherland asynchronous micro-pipeline architecture 100. The Sutherland asynchronous micro-pipeline architecture is one form of asynchronous micro-pipeline architecture that uses a handshaking protocol built by Muller-C elements to control the micro-pipeline building blocks. The architecture 100 includes a plurality of computing logic 102 linked in sequence via flip-flops or latches 104 (e.g., registers). Control signals are passed between the computing blocks via Muller C-elements 106 and delayed via delay logic 108. Further information describing this architecture 100 is published by Ivan Sutherland in Communications of the ACM Volume 32 Issue 6, June 1989 pages 720-738, ACM New York, N.Y., USA, which is incorporated herein by reference.
Now turning to FIG. 2, there is illustrated a typical section or processing stage of a synchronous system 200. The system 200 includes flip-flops or registers 202, 204 for clocking an output signal (data) 206 from a logic block 210. On the right side of FIG. 2 there is shown an illustration of the concept of meta-stability. Set-up times and hold times must be considered to avoid meta-stability. In other words, the data must be valid and held during the set-up time and the hold time, otherwise a set-up violation 212 or a hold violation 214 may occur. If either of these violations occurs, the synchronous system may malfunction. The concept of meta-stability also applies to asynchronous systems. Therefore, it is important to design asynchronous systems to avoid meta-stability. In addition, like synchronous systems, asynchronous systems also need to address various potential data/instruction hazards, and should include a bypassing mechanism and pipeline interlock mechanism to detect and resolve hazards.
Accordingly, there are needed asynchronous processing systems, asynchronous processors, and methods of asynchronous processing that are stable, and detect and resolve potential hazards (i.e., remove meta-stability).